Allows you to examine and optionally modify the contents of NPX and CPU registers such as the thread state segment.
x [n] x [[cpu-reg][.bitname][=expression]] x [[npx-reg][=hex#|real#]] x tss [(expression)][.reg[=expression]]For an example, click here.
If you use the x command with no parameters, SDM displays the current contents of the CPU registers with respect to your application at the time the fault, trap, or break occurred.
n
cpu-reg
If you do not include any other parameters, SDM displays the contents of the register or bit followed by a dash (-) prompt. At this point, to change the register or bit value, enter the new value followed by a <CR>. If you do not want to change the value, enter a <CR>.
The register abbreviations you can enter are listed below. Not all registers may be accessible on your CPU. For example, CR4 is not defined on the Intel386 microprocessor. Abbreviations include:
Register type | 32-bit | 16-bit | 8-bit | |
---|---|---|---|---|
General Registers | EAX EBX ECX EDX EBP ESI EDI |
AX BX CX DX BP SI DI |
AH BH CH DH |
AL BL CL DL |
Stack Pointer | ESP | SP | ||
Code Segment | CS | |||
Data Segment | DS | |||
Stack Segment | SS | |||
Extra Data Segments | ES FS GS |
|||
Flag Register | EFL | FL | ||
Instruction Pointer | EIP | IP | ||
Control Registers | CR0 CR1 CR2 CR3 CR4 |
MSW |
The FL, EFL, MSW, CR0, CR3, and CR4 registers are special registers containing bit fields. SDM displays the contents of these registers first with the binary values and a mnemonic for each bit field, then as a hexadecimal word value. For example, the display of EFL might be as follows, where 0 or 1 as a mnemonic indicates a reserved bit field:
ID VIP VIF AC VM RF 0 NT IOPL OF DF IF TF SF ZF 0 AF 0 PF 1 CF 0 0 0 0 0 0 0 0 00 0 0 1 0 0 1 0 0 0 1 1 0 00000246 -
The mnemonics for bit fields in the special registers are listed below.
EFL & FL | Bit Names | CR0 & MSW | Bit Names |
---|---|---|---|
AC | Alignment Check | AM | Alignment Mask |
AF* | Auxiliary Carry Flag | CD | Cache Disable |
CF* | Carry Flag | EM** | Emulation Mode (Coprocessor) |
DF* | Direction Flag | ET** | Extension Type |
IF* | Interrupt Enable Flag | MP** | Math Present (Monitor Coprocessor) |
ID | Identification Flag | NE | Numerics Exception |
IOPL* | I/O Privilege Level (2 bits) | NW | Not Write-Through |
NT* | Nested Thread Flag | PE** | Protection Enable |
OF* | Overflow Flag | PG | Paging Enable |
PF* | Parity Flag | TS** | Thread Switch |
RF | Resume Flag | WP | Write Protect |
SF* | Sign Flag | CR3 | Bit Names |
TF* | Trap Enable Flag | PCD | Page Cache Disable |
VIF | Virtual Interrupt Flag | PWT | Page Write-Through |
VIP | Virtual Interrupt Pending | (no mnemonic) | Physical base addres of page director table in bits 12-31 |
VM | Virtual 8086 Mode | CR4 | Bit Names |
ZF* | Zero Flag | DE | Debugging Extensions |
MCE | Machine Check Enable | ||
PSE | Page Size Extensions | ||
PVI | Protected mode Virtual Interrupt | ||
TSD | Time Stamp Disable | ||
VME | Virtual 8086 Mode Extensions |
* Bit fields in the Flags register (FL), which is a subset of EFL
** Bit fields in the Machine Status Word (MSW), which is a subset of CR0
.bitname
cpu-reg
name with a period (.) and the mnemonic for the bit field. For example, to display only the Carry Flag from the Extended Flags register, you would enter: x efl.cr
=expression
expression
parameter instructs SDM to place the value in the register.
npx-reg
Register Name | Abbreviation | Register Name | Abbreviation |
---|---|---|---|
NPX State | N | Status Word | SW |
Control Word | CW | Tag Word | TW |
Instrution Pointer | IP* | Data Pointer | DP* |
Stack Register 0 | ST(0) | Stack Register 4 | ST(4) |
Stack Register 1 | ST(1) | Stack Register 5 | ST(5) |
Stack Register 2 | ST(2) | Stack Register 6 | ST(6) |
Stack Register 3 | ST(3) | Stack Register 7 | ST(7) |
* These registers cannot be modified.
If you do not include any further parameters, SDM displays the contents of the NPX register followed by a dash (-) prompt.
At this point, to change the register value, you can enter a value. Enter stack register values as real numbers; enter all other NPX registers values as words. You cannot modify the IP and DP registers for the NPX. If you do not want to change the NPX register value or display any further NPX register contents, enter a <CR>.
hex#
real#
tss
To access TSS registers, use this parameter. If you do not include any further parameters, SDM displays the current contents of the TSS whose selector is in the TR register.
Name | Abbreviation |
---|---|
Local Descriptor Table Register | LDTR |
Interrupt Descriptor Table Register | IDTR |
Global Descriptor Table Register | GDTR |
Thread Register | TR |
Link to Nested Thread | LINK |
Level 0 Stack Segment | SS0 |
Level 1 Stack Segment | SS1 |
Level 2 Stack Segment | SS2 |
Level 0 Stack Pointer | ESP0 |
Level 1 Stack Pointer | ESP1 |
Level 2 Stack Pointer | ESP2 |
(expression)
If you do not include any further parameters, SDM displays the contents of the indicated TSS.
.reg
If you do not include any further parameters, SDM displays the contents of the register in the TSS followed by a dash (-) prompt.
At this point, to change the TSS component register value, enter the new value followed by a <CR>. If you do not want to change the TSS contents, enter a <CR>.
If you use the x command with both a register name and an expression, the modification you specify takes place immediately and SDM does not display the new value. If you redisplay the NPX state (after modification), SDM displays the results of the change you made.
You can use the x command to set the registers or the TSS contents to any value. If you use any invalid values, SDM reports them and does not execute the change.
..x
SDM responds with this display:
EAX=0000FFFF CS=1000 EIP=00000000 EFL=00000000 LDTR=2A0 EBX=0000FFFF SS=0000 ESP=00000428 BP=0000FFFF TR=278 ECX=0000FFFF DS=0000 ESI=0000FFFF FS=0000 MSW=FFF0 EDX=0000FFFF ES=0000 EDI=0000FFFF GS=0000 GDTR .BASE=00000000 .LIMIT=0000 IDTR .BASE=00000000 .LIMIT=0000
..xn
SDM responds:
CW: X X X IC R C P C IM X PM UM OM ZM DM IM 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 IP = 00000:0000 SW: B C3 T O P C2 C1 C0 IR X PE UE OE ZE DE IE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TW: T 7 T 6 T 5 T 4 T 3 T 2 T 1 T 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 1 DP = 00000:0000 ST(0) ZERO 00000000000000000000R 0 ST(1) VALID 3FFF999999999999999AR 1.2 ST(2) VALID BFFF999999999999999AR -1.2 ST(3) SPECIAL FFFF0000000000000000R -Infinity ST(4) SPECIAL 7FFFFF00000000000000R +NAN ST(5) EMPTY 4000C90FDA9E46A7843ER 3.14159265 ST(6) VALID 4CF5F08B8D41AF800AC8R 1.23456E+999 ST(7) VALID 3FFF1800000000000000R .1875 UNNORM 3 BITS
See also
CW, SW, and TW output fields, in the hardware reference manual for your microprocessor
..x tss(68)
SDM responds:
EAX=00001234 CS=0020 EIP=00000000 EFL=00000000 LDTR=02D0 LINK=0058 EBX=00001234 SS=0000 ESP=00000428 EBP=0000FFFF SS0=0020 ESP0=0000FFFE ECX=00001234 DS=0000 ESI=0000FFFF FS=0000 SS1=0000 ESP1=00000000 EDX=00001234 ES=0000 EDI=0000FFFF GS=0000 SS2=0000 ESP2=00000000